(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to reduce out diffusion of ion implanted dopants from a polysilicon gate structure during a procedure used to activate the ion implanted dopants.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices with sub 0.25 um features, has allowed the performance of the sub 0.25 um devices to be increased while reducing the fabrication cost of a semiconductor chip comprised with sub-0.25 um features. The smaller device features result in a reduction of performance degrading parasitic capacitance, while the greater number of smaller semiconductor chips comprised with sub-0.25 um features, obtained from a specific size starting substrate, reduce the fabrication cost of an individual semiconductor chip. However specific features of a semiconductor device, such as a gate structure of a metal oxide semiconductor field effect transistor (MOSFET), device, can encounter problems when defined at widths as narrow as 0.25 um. For example the dopants in a gate structure such as a polysilicon gate structure, can be placed in the narrow width polysilicon gate structure via ion implantation procedures performed in a blanket polysilicon layer prior to gate definition. Activation of the implanted ions has to be performed to result in the desired gate structure conductivity, however the anneal procedure used for dopant activation can result in loss of implanted dopants via out diffusion from the top surface of the blanket polysilicon layer, or via out diffusion from the top surface as well as the sides of a defined polysilicon gate structure. The loss of implanted dopants will result in a less conductive gate structure thus reducing MOSFET performance.
The present invention will describe a process sequence in which the out diffusion of implanted dopants in a defined gate structure is reduced via use of a blanket insulator layer wherein the same insulator layer will be defined as a component of a composite insulator spacer on the sides of the gate structure after activation of the implanted dopants. Prior art such as Nandakumar, in U.S. Pat. No. 6,362,062 B1, Tseng et al, in U.S. Pat. No. 6,063,698, Pfiester, in U.S. Pat. No. 5,201,354, and Chien et al, in U.S. Pat. No. 6,248,623 B1, describe methods of forming offset spacers on the sides of a defined gate structure. However none of these prior art describe the process sequence featured in this present invention in which the blanket insulator layer, to subsequently be defined as a offset spacer of a composite insulator spacer, is used to reduce dopant out diffusion from all exposed surface of a gate structure during the dopant activation anneal procedure.